The mechanism of the aging and/or failure of N-MOS transistors caused by the phenomenon of impact ionization taking place under particular bias conditions of the gate of the transistor versus its source while the drain is biased at a relatively high voltage in respect to the source potential, is well known and debated in literature.
This problem occurs every time a N-MOS transistor having its drain biased at the supply voltage by a preceding switching on of the P-MOS transistor portion of a CMOS inverter, switches on as a consequence of a raising of the gate voltage. The flow of electrons crossing the channel region of the transistor is accelerated by a synergistic combination of electric fields due to the "summing" of the effects of the V.sub.GS and V.sub.DS voltages. This causes additional carriers to be driven to the drain coming from electron-hole pairs generated by the impact of high kinetic energy electrons with orbitant electrons of the atoms of the crystal lattice in the drain region. This mechanism generates an additional current known as "substrate current" which adds to the drain-source current. This additional current is highly dangerous because even if a low level (in the order of few .vertline.A) may produce locally a direct biasing of the substrate in respect to the source region of the transistor, thus triggering on a parasitic bipolar transistor in parallel to the real N-MOS. The V.sub.DS voltage to which this parasitic bipolar transistor switches on is known in literature as the snap-back voltage. This phenomenon may be destructive for the metallic connections (contacts) of the N-MOS, which must convey a far augmented current than the design current. Even where complete failure is avoided, the mechanism at the base of the snap-back phenomenon is such as to cause in time a degradation of the electrical characteristics of the N-MOS transistor. This degradation (aging) due to the presence of high energy electrons in the channel, is cumulative in time, thus producing a progressive loss of functionality of the N-MOS transistors which is even more feared than an instantaneous failure, because the "microscopic" behavior of the integrated circuit varies with time due to the alterations which have occurred at the level of single N-MOS devices, the threshold voltage (V.sub.th) and transconductance (gm) of which tend to subtly change with time.
It is known that impact ionization and its negative effects may be countered by forming graded drain diffusions (known also as drain extensions). These graded drain diffusions may be obtained by forming a second diffused region having a lower dopant concentration than that commonly used for the drain region proper. The use of drain extensions results in increasing the V.sub.DS voltage to which the snap-back phenomenon takes place and reducing the aging process caused by impact ionization, by creating, during the switching on the N-MOS transistor, an electric field of reduced intensity near the drain region of the transistor by virtue of the graded diffusion. Frequently in certain circuit applications, it is necessary for the same prevention reasons, to also form the source diffusion in a similarly graded manner, i.e., provide the N-MOS transistor with "bilateral" (drain) extensions.
The raising of the snap-back voltage causes a reduction of the electrical performance of the N-MOS transistor that is provided with drain extensions, in terms of reduced speed and increased ON-resistance.
Moreover, under the aspect of the fabrication technology of these devices, the necessary use of a dedicated "drain extension" mask, beside complicating the fabrication process, makes the N-MOS transistors more cumbersome in terms of layout and more sensitive to misalignment problems and therefore more difficult to be reduced in size through compacting technologies, also known as "shrinkage processes," toward which any circuit evolves in time for exploiting the improvements that the photolithographic techniques and apparatuses constantly go through.
Thus, while using drain and source extensions solve some problems, it creates new problems, including reduced speed performance and increased power requirement.
All the above-mentioned problems are most frequently encountered in mixed analog-digital integrated CMOS circuits, wherein two different supply voltages are normally present: a low supply voltage (5 V) for the internal logic circuitry which interfaces with the analog portions of the integrated circuit operating at such a higher supply voltage in order to ensure a large dynamic voltage swing.
The logic circuits operating at high supply voltage are therefore potentially sensitive to said snap-back problems constitute parts of the integrated circuit which, because of the large use of graded junctions, raise remarkable problems of increased criticality when attempting a compacting of the integrated circuit for exploiting at best improved fabrication techniques which may have become available.
Therefore, there is a need of logic circuits, i.e., for CMOS logic gates, capable of operating at a relatively high supply voltage and wherein the need of forming graded diffusions in the structure of N-MOS transistors be minimized in order to maintain characteristics of high speed for the propagation of data through the logic gates and ensuring a low internal ON-resistance of the same transistors.
The present invention provides an effective solution to this specific technical problem.